オール・トランジスタ4ビットCPUの製作とFPGA開発
[Vol.5 ステート・マシンと命令デコーダの設計]

`default_nettype none

module STATE_MACHINE
(
	input wire clk,
	input wire n_rst,
	input wire pc_ld,
	
	output wire ld_en,
	output wire pc_up
);

reg state;

always@(posedge clk, negedge n_rst)
begin
	if(~n_rst)
		state <= 1'b0;
	else if (pc_ld)
		state <= 1'b0;
	else
		state <= ~state;
end

assign ld_en = ~state;
assign pc_up = state;

endmodule

`default_nettype wire

`timescale 1us/10ns

module tb_state_machine();

//wire, register declaration
reg clk;
reg n_rst;
reg [7:0] cycle_cnt;

reg pc_ld;
wire ld_en;
wire pc_up;

//clock signal
initial clk = 1'b0;
always #0.5
	clk = ~clk;

//reset signal
initial begin
	n_rst = 1'b0;
	#1;
	n_rst = 1'b1;
end


//pc load signal
initial begin
	pc_ld = 1'b0;
	#4;
	pc_ld = 1'b1;
end

//cycle count
initial cycle_cnt = 0;
always @ (posedge clk)
	cycle_cnt = cycle_cnt + 8'd1;

//stop
always @ (*)
if(cycle_cnt == 8'd10)
	$stop;

//STATE_MACHINE instance
STATE_MACHINE state_machine
(
	.clk(clk),
	.n_rst(n_rst),
	.pc_ld(pc_ld),
	.ld_en(ld_en),
	.pc_up(pc_up)
);

endmodule

#transcript window setting
transcript on

#delete "rtl_work" directory
if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}

#create the design library
vlib rtl_work

#define a mapping between logical and physical library name
vmap work rtl_work

#compile the Verilog files
vlog  -vlog01compat -work work \
	+incdir+../../ \
	../../STATE_MACHINE.v \
	./tb_state_machine.v

#invoke the simulator
vsim -L altera_mf_ver -c work.tb_state_machine

#wave window setting
add wave -divider TEST_BENCH
add wave -bin sim:/tb_state_machine/clk
add wave -bin sim:/tb_state_machine/n_rst
add wave -unsigned sim:/tb_state_machine/cycle_cnt

add wave -divider STATE_MACHINE_INPUT
add wave -bin sim:/tb_state_machine/state_machine/pc_ld


add wave -divider STATE_MACHINEOUTPUT
add wave -bin sim:/tb_state_machine/state_machine/ld_en
add wave -bin sim:/tb_state_machine/state_machine/pc_up


#save all signal
log -r *

#run simulation
run -all

#wave window zoom setting
wave zoom full

`default_nettype none

module ID
(
	input wire [3:0] d,
	input wire ld_en,
	input wire c,
	input wire z,
	
	output wire a_reg_ld,

	output wire b_reg_ld,
	output wire b_reg_oe, //"ROM_OE" is "~B_REG_OE"

	output wire alu_as,
	output wire alu_oe, //"IN_OE" is "~ALU_OE"
	output wire alu_ld,
	output wire alu_mux_a,
	output wire alu_mux_b,

	output wire out_ld,

	output wire pc_ld,

	output wire n_halt
);

//=====================================
//A REG Load Enable
//=====================================
assign a_reg_ld = func_a_reg_ld(d, ld_en);
function func_a_reg_ld;
	input [3:0] d;
	input ld_en;
	begin 
		casex(d)
			4'b00x0: func_a_reg_ld = ld_en;
			4'b01xx: func_a_reg_ld = ld_en;
			4'b1011: func_a_reg_ld = ld_en;
			default: func_a_reg_ld = 1'b0;
		endcase
	end
endfunction

//=====================================
//B REG Load Enable
//=====================================
assign b_reg_ld = func_b_reg_ld(d, ld_en);
function func_b_reg_ld;
	input [3:0] d;
	input ld_en;
	begin 
		casex(d)
			4'b0001: func_b_reg_ld = ld_en;
			4'b0011: func_b_reg_ld = ld_en;
			default: func_b_reg_ld = 1'b0;
		endcase
	end
endfunction

//=====================================
//B REG Output Enable
//=====================================
assign b_reg_oe = func_b_reg_oe(d);
function func_b_reg_oe;
	input [3:0] d;
	begin 
		casex(d)
			4'b001x: func_b_reg_oe = 1'b1;
			4'b010x: func_b_reg_oe = 1'b1;
			4'b100x: func_b_reg_oe = 1'b1;
			4'b1011: func_b_reg_oe = 1'b1;
			default: func_b_reg_oe = 1'b0;
		endcase
	end
endfunction

//=====================================
//ALU ADD/SUB
//=====================================
assign alu_as = func_alu_as(d);
function func_alu_as;
	input [3:0] d;
	begin 
		casex(d)
			4'b01x1: func_alu_as = 1'b1;
			default: func_alu_as = 1'b0;
		endcase
	end
endfunction

//=====================================
//ALU Output Enable
//=====================================
assign alu_oe = (d == 4'b1011) ? 1'b0 : 1'b1;

//=====================================
//ALU Load Enable
//=====================================
assign alu_ld = func_alu_ld(d, ld_en);
function func_alu_ld;
	input [3:0] d;
	input ld_en;
	begin 
		casex(d)
			4'b01xx: func_alu_ld = ld_en;
			default: func_alu_ld = 1'b0;
		endcase
	end
endfunction

//=====================================
//ALU MUX A
//=====================================
assign alu_mux_a = func_alu_mux_a(d);
function func_alu_mux_a;
	input [3:0] d;
	begin 
		casex(d)
			4'b0011: func_alu_mux_a = 1'b1;
			4'b01xx: func_alu_mux_a = 1'b1;
			4'b1000: func_alu_mux_a = 1'b1;
			default: func_alu_mux_a = 1'b0;
		endcase
	end
endfunction

//=====================================
//ALU MUX B
//=====================================
assign alu_mux_b = func_alu_mux_b(d);
function func_alu_mux_b;
	input [3:0] d;
	begin 
		casex(d)
			4'b0011: func_alu_mux_b = 1'b0;
			4'b1000: func_alu_mux_b = 1'b0;
			default: func_alu_mux_b = 1'b1;
		endcase
	end
endfunction

//=====================================
//OUT REG Load Enable
//=====================================
assign out_ld = func_out_ld(d, ld_en);
function func_out_ld;
	input [3:0] d;
	input ld_en;
	begin 
		casex(d)
			4'b100x: func_out_ld = ld_en;
			4'b1010: func_out_ld = ld_en;
			default: func_out_ld = 1'b0;
		endcase
	end
endfunction

//=====================================
//Program Counter Load Enable
//=====================================
assign pc_ld = func_pc_ld(d, c, z);
function func_pc_ld;
	input [3:0] d;
	input c;
	input z;
	begin 
		casex(d)
			4'b1100: func_pc_ld = 1'b1;
			4'b1101: func_pc_ld = ~c;
			4'b1110: func_pc_ld = ~z;
			default: func_pc_ld = 1'b0;
		endcase
	end
endfunction

//=====================================
//HALT
//=====================================
assign n_halt = (d == 4'b1111)? 1'b0 : 1'b1;

endmodule

`default_nettype wire

`timescale 1us/10ns

module tb_id();

//wire, register declaration
reg clk;
reg [7:0] cycle_cnt;

reg [3:0] d;
reg ld_en;
reg c;
reg z;

wire a_reg_ld;
wire b_reg_ld;
wire b_reg_oe;
wire alu_as;
wire alu_oe;
wire alu_ld;
wire alu_mux_a;
wire alu_mux_b;
wire out_ld;
wire pc_ld;
wire n_halt;

//clock signal
initial clk = 1'b0;
always #0.5
	clk = ~clk;

//data (instruction)
initial d = 0;
always @ (posedge clk)
	d = d + 4'd1;

//register load signal
initial begin
	ld_en = 1'b1;
end

//carry flag from ALU
initial begin
	c = 1'b0;
end

//zero flag from ALU
initial begin
	z = 1'b0;
end

//cycle count
initial cycle_cnt = 0;
always @ (posedge clk)
	cycle_cnt = cycle_cnt + 8'd1;

//stop
always @ (*)
if(cycle_cnt == 8'd16)
	$stop;

//ID instance
ID id
(
	.d(d),
	.ld_en(ld_en),
	.c(c),
	.z(z),

	.a_reg_ld(a_reg_ld),

	.b_reg_ld(b_reg_ld),
	.b_reg_oe(b_reg_oe),

	.alu_as(alu_as),
	.alu_oe(alu_oe),
	.alu_ld(alu_ld),
	.alu_mux_a(alu_mux_a),
	.alu_mux_b(alu_mux_b),

	.out_ld(out_ld),
	
	.pc_ld(pc_ld),

	.n_halt(n_halt)
);

endmodule

#transcript window setting
transcript on

#delete "rtl_work" directory
if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}

#create the design library
vlib rtl_work

#define a mapping between logical and physical library name
vmap work rtl_work

#compile the Verilog files
vlog  -vlog01compat -work work \
	+incdir+../../ \
	../../ID.v \
	./tb_id.v

#invoke the simulator
vsim -L altera_mf_ver -c work.tb_id

#wave window setting
add wave -divider TEST_BENCH
add wave -bin sim:/tb_id/clk
add wave -unsigned sim:/tb_id/cycle_cnt

add wave -divider ID_INPUT
add wave -bin sim:/tb_id/id/d
add wave -bin sim:/tb_id/id/ld_en
add wave -bin sim:/tb_id/id/c
add wave -bin sim:/tb_id/id/z

add wave -divider ID_AREG_OUTPUT
add wave -bin sim:/tb_id/id/a_reg_ld

add wave -divider ID_BREG_OUTPUT
add wave -bin sim:/tb_id/id/b_reg_ld
add wave -bin sim:/tb_id/id/b_reg_oe

add wave -divider ID_ALU_OUTPUT
add wave -bin sim:/tb_id/id/alu_as
add wave -bin sim:/tb_id/id/alu_oe
add wave -bin sim:/tb_id/id/alu_ld
add wave -bin sim:/tb_id/id/alu_mux_a
add wave -bin sim:/tb_id/id/alu_mux_b

add wave -divider ID_OUT_OUTPUT
add wave -bin sim:/tb_id/id/out_ld

add wave -divider ID_PC_OUTPUT
add wave -bin sim:/tb_id/id/pc_ld

add wave -divider ID_HALT_OUTPUT
add wave -bin sim:/tb_id/id/n_halt

#save all signal
log -r *

#run simulation
run -all

#wave window zoom setting
wave zoom full